摘 要
如今，集成电路技术发展的速度越来越快,不但使得在单个集成电路板上所能集成的晶体管数越来越多,同时也推动了嵌入式系统由过去的板级时代进入现在片上系统时代，也就是我们所说的SOC时代。本论文就是基于FPGA的精简指令集CPU的设计。CPU是SOC的核心,如何设计高质量的处理器系统成为了片上系统中的核心问题。片上系统是在一个微小的芯片上集成数以万计的晶体管。当今CPU的设计形式分为复杂指令集设计和精简指令集设计。复杂指令集的指令集系统过于复杂，不利于提高系统的性能，也容易导致设计失误。而精简指令集可以较好的解决问题，是现在CPU设计所采用的主流方法。
本论文所设计RISC_CPU是16位的，共分八个模块，内含16条指令，运用多种寻址方式，使用QuartusII进行设计,并用Modelsim进行功能仿真。主要将RISC_CPU的结构、指令系统和寻址方式，运行方式以及最后各个模块的调试和时序分析做了系统化阐述。
设计采用可编程技术实现硬件电路，并用Verilog对RISC_CPU各模块进行编程实现。从仿真的结果能够看出处理器可以稳定的执行系统指令，每条指令刚好能够在规定的时钟周期执行完毕。由QuartusII跑出时序报告，整个过程没有出现时序违例现象，满足时序要求。达到了本论文的预期设计要求。
关键词 CPU、RISC、Verilog、时序仿真、功能仿真、FPGA
Abstract
Today, integrated circuit technology development faster and faster, not only makes the integration of transistors on a single integrated circuit board can number more and more, also promoted the embedded system from the past era of board level into the era of on-chip system now, also is what we call the SOC era.This paper is based on the FPGA's compact instruction set CPU design.The CPU is the core of SOC, and how to design a high quality processor system becomes a core problem in the system.The system is integrated with tens of thousands of transistors on a tiny chip.Today the design of cpus is divided into complex instruction set design and compact instruction set design.The instruction set system of complex instruction sets is too complicated to improve the performance of the system and can easily lead to design failure.While streamlining instruction sets can be a good solution to the problem, it is the main method adopted by CPU design.
The design of the risc_cpus in this paper is 16 bits, with eight modules, including 16 instructions, using a variety of addressing modes, using QuartusII for design, and using Modelsim for functional simulation.The structure, command system and addressing mode of the RISC_CPU, the debug and the sequential analysis of the final modules are systematically described.
The design USES programmable technology to implement the hardware circuit, and the RISC_CPU modules are programmed by Verilog.The result of the simulation shows that the processor can reliably execute the system instructions, each of which can be executed at the specified clock cycle.QuartusII runs out of sequence reports, and there is no sequence of violations in the whole process, which satisfies the sequence requirements.The design requirements of this paper are met.
Keywords CPU, RISC, Verilog, sequential simulation, functional simulation, FPGA
1.1 课题背景
自从神威太湖之光问世之后，我就对CPU充满了好奇，希望有一天可以自己动手做一个简单的CPU，刚好通过这次毕业设计，我有机会实现这一想法，就是做一个简单一点的CPU。CPU有许多繁琐复杂的功能，不仅能够处理运算系统中数据，还能够执行计算机指令。根据CPU处理能力的级别不同，它执行程序的速度也会不同。在计算机中CPU的职责就是读取全部的操作命令。CPU是计算机的中枢神经，对计算机发出的每一条指令都予以编译和执行。
早期的处理器运算能力不够，想要在规定的时间内完成指定的计算量只能使用机器语言指令比较少的复杂指令集结构。导致早期的处理器运算能力不够。所以早期的CPU几乎全是复杂指令集架构。虽然复杂指令集架构有利于开发编译器，但它对工艺设计要求较高，同时也会因为处理器更加复杂而降低使用效率。CPU的操作步骤通常用软件编写，所以编译器的效率较高。精简指令集就是用这种设计思路编写的。这种方法不仅可以使指令功能得到化简还可以提高指令的并行程度。精简指令集采用更容易实现的寻址方式。使用功能简单，指令数目更少的方式来实现。精简指令集将复杂的功能用一段程序表示，为了提高CPU的频率而减少指令的执行周期。简单的算法直接依靠通用寄存器来提高运算速度。
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